All projects
Digital design
Pipelined CPU in Verilog
Custom-ISA pipelined processor in Xilinx Vivado
CourseworkJan 2025 - Mar 2025Completed
VerilogVivadoCPUpipelining
A pipelined CPU with a custom instruction set optimized for arithmetic, a forwarding unit for pipeline efficiency, and hazard detection, validated through simulation and performance analysis.
- 01Custom instruction set optimized for arithmetic operations
- 02Forwarding unit and hazard detection
- 03Validated via simulation and performance analysis in Vivado ML
Designed and implemented a pipelined processor in Xilinx Vivado ML with a custom arithmetic-optimized instruction set, a forwarding unit to keep the pipeline fed, and hazard detection. Verified through simulation and performance analysis.